Patsis George P.

 

patsis		              

Office:  Α118, Building Α, Αncient Οlive-grove Campus
Work phone: +30 210 538-1545

Lab:
Lab phone: 
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Webpage: http://microsenses.eee.uniwa.gr/

Office hours: Monday (7.00-8.30), Tuesday (7.00-8.30, 11.30-12.30), Wednesday (7.00-10.30, 13.30-15.00)

 

Discipline: DESING AND SIMULATION OF MICROELECTRONIC DEVICES

 

Studies

1999 - PhD in Physics, Department of Applied Physical and Mathematical Sciences, National Technical University of Athens. 
1998 - Master's Degree in Electronic Automation, Department of Informatics, University of Athens.  
1997 - Master's Degree in Microelectronics, Department of Informatics, University of Athens. 
1995  - Degree in Physics, Department of Physics, University of Athens.

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Research interests

  • Design - simulation - fabrication of microelectronic devices and integrated circuits. 
  • Analog/Digital electronics.
  • Algorithms / Modelling / Programming Languages.
  • Numerical Analysis.
  • Applied Mathematics.

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Representative Publications

  1. Evolution of Resist Roughness during Development: Stochastic Simulation and Dynamic Scaling Analysis, V. Constantoudis, G. P. Patsis, and E. Gogolides, J. Micro/Nanolith. MEMS MOEMS 9, 41207 (2011).Performance simulation, realization and evaluation of capacitive sensor arrays for the real time detection of volatile organic compounds, P. Oikonomou, G.P. Patsis, A. Botsialas, K. Manoli, D. Goustouridis, N.A. Pantazis, A. Kavadias, E. Valamontes, Th. Ganetsos, M. Sanopoulou, I. Raptis, Microelec. Engin. 88(8), 2395 (2011)
  2. Chemocapacitance response simulation through polymer swelling and capacitor modeling, P. Oikonomou, A. Salapatas, K. Manoli, K. Misiakos, D. Goustouridis, E. Valamontes, M. Sanopoulou, I. Raptis, G. P. Patsis, Procedia Engineering, Volume 25, 2011, Pages 423-426.
  3. Hybrid integration of microfabricated chemcapacitor arrays with miniaturized read-out electronics towards low-power gas sensing module, P. Oikonomou, G. P. Patsis, K. Manoli, D. Goustouridis, E. Valamontes, N. Pantazis, M. Sanopoulou, I. Raptis, Procedia Engineering, Volume 25, 2011, Pages 1117-1120.
  4. Simulation and Experimental Evaluation of Gas Mass Flow Transfer Rate in Microchannels, G. P. Patsis, K. Ninos, D. Mathioulakis, and G. Kaltsas, Procedia Engineering, Volume 25, 2011, Pages 447-450.
  5. Fractals and device performance variability: The key role of roughness in micro and nanofabrication Pages 121-125 V. Constantoudis, G.P. Patsis, E. Gogolides Microelec. Engin. Volume 90, Pages 1-172 (February 2012)
  6. Chemocapacitor performance modeling by means of polymer swelling optical measurements, P. Oikonomou, A. Botsialas, K. Manoli, D. Goustouridis, E. Valamontes, M. Sanopoulou, I. Raptis, G.P. Patsis, Sensors and Actuators B: Chemical, Volumes 171–172, August–September 2012, Pages 409-415.
  7. Modelling and evaluation of a thermal microfluidic sensor fabricated on plastic substrate, G. P. Patsis, A. Petropoulos, G. Kaltsas in Microsystem Technologies 18(3) 359 (2012).
  8. Room temperature analysis of Ge p+/n diodes reverse characteristics fabricated by platinum assisted dopant activation, V. I.-Sougleridis, N. Poulakis, P. Dimitrakis, P. Normand, G. P. Patsis, A.Dimoulas, E. Simoen Solid-State Electronics, Volume 81, March 2013, Pages 19-26 (2013).
  9. Gas-mass-flow transfer-rate simulation and experimental evaluation in microchannels, G. P. Patsis, K. Ninos, D. Mathioulakis, and G. Kaltsas, Microsystem Technologies: Volume 19, Issue 12 Page 1919-1925 (2013).
  10. Process-simulation-flow and metrology of VLSI layout fine-features, G. P. Patsis, IOSR Journal of VLSI and Signal Processing, vol. 7, no. 6, 2017, pp. 23-28.
  11. VHDL-AMS macromodels of MOSFET. Consideration of gate length variability and single-electron-transistors, G. P. Patsis, IOSR Journal of VLSI and Signal Processing , vol. 7, no. 6, 2017, pp. 29-33.
  12. Basic topologies of MOS single-stage amplifiers. DC analysis for maximum input-voltage swing and amplification, G. P. Patsis, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 1, 2018, pp. 47-59.
  13. MOSFET EKV Verilog-A model implementation in Genesys, G. P. Patsis, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 2, 2018, pp. 73-86.
  14. Educational Introduction to VLSI Layout Design with Microwind, G. P. Patsis, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 5, 2018, pp. 18-29.
  15. Educational Introduction to CMOS Circuit Design with Texas Instrument ANalyzer (TINA). Applications in Design of Digital CMOS Gates G. P. Patsis, IOSR Journal of VLSI and Signal Processing, vol. 8, no. 5, 2018, pp. 39-48.

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Undergraduate Courses

  • Digital System Design (3rd semester)
  • Data Structures and Algorithms (5th semester)
  • Design of CMOS VLSI  (7th semester)

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Postgraduate Courses

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Curriculum Vitae

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